Minimisation of Test Application time in the scan technique
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Date
January, 2010
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Abstract
The focus of this study is on how test application time in the scan technique can
be minimised. A novel method of how this can be achieved, called the Vector
Match Approach, is presented. It takes advantage of matching patterns in test
vectors, by rearranging them such that those with matching patterns are closer
to each other. Flow charts describing the logic of the algorithm and an example,
illustrating how it works are also shown. In addition, the circuit architecture for
the Vector Match Approach is presented. It incorporates a scan register and a
multiple-input signature register (MISR) together with the circuit under test.
Description
A Thesis submitted to the Department of Telecommunication
Engineering, Kwame Nkrumah University of Science and Technology in partial ful lment of the requirements for the degree of Master of Science