Automatic Test Pattern Generation for Iterative Logic Arrays

Abstract

In this work, measures to evaluate fault-effect propagation of test patterns of a C-test are first formulated. Next, the repetition property of the test patterns is exploited to develop a method for generating C-tests for ILAs under the cell fault model. Based on the results of test generation, the method identifies points of insertion of extra hardware in order to achieve C-testability for the target array. Finally, results obtained by applying the proposed method to generate minimum C-tests for a few well-known arithmetic arrays are shown.