Minimisation of Test Application time in the scan technique
| dc.contributor.author | Opare Adu-Boahen, Kwasi | |
| dc.date.accessioned | 2011-07-15T14:53:06Z | |
| dc.date.accessioned | 2023-04-20T02:50:18Z | |
| dc.date.available | 2010-07-15T14:53:06Z | |
| dc.date.available | 2023-04-20T02:50:18Z | |
| dc.date.issued | January, 2010 | |
| dc.description | A Thesis submitted to the Department of Telecommunication Engineering, Kwame Nkrumah University of Science and Technology in partial ful lment of the requirements for the degree of Master of Science | en_US |
| dc.description.abstract | The focus of this study is on how test application time in the scan technique can be minimised. A novel method of how this can be achieved, called the Vector Match Approach, is presented. It takes advantage of matching patterns in test vectors, by rearranging them such that those with matching patterns are closer to each other. Flow charts describing the logic of the algorithm and an example, illustrating how it works are also shown. In addition, the circuit architecture for the Vector Match Approach is presented. It incorporates a scan register and a multiple-input signature register (MISR) together with the circuit under test. | en_US |
| dc.identifier.uri | https://ir.knust.edu.gh/handle/123456789/364 | |
| dc.language.iso | en | en_US |
| dc.title | Minimisation of Test Application time in the scan technique | en_US |
| dc.type | Article | en_US |
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