Design of a fully integrated VHF CP-PLL frequency synthesizer with an all-digital defect-oriented built-in self-test
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Date
2022-10-28
Journal Title
Journal ISSN
Volume Title
Publisher
The Journal of Engineering
Abstract
This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL)
with a fully digital defect-oriented built-in self-test (BIST) for very-high frequency (VHF)
applications. The frequency synthesizer has a 40–100 MHz tuning range and uses a ring
voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of
−132 dBc/Hz at 1 MHz and consumes 1.8mWon a 3 V supply. The BIST implementation
uses fewer external input or output, is capable of efficient fault diagnosis, and is compact,
posing a low area overhead. The integrated circuit design was realized in the AMI 0.6μ
complementary metal-oxide-semiconductor process.