Design of a fully integrated VHF CP-PLL frequency synthesizer with an all-digital defect-oriented built-in self-test
| dc.contributor.author | Kommey, Benjamin | |
| dc.contributor.author | Boateng, Kwame Osei | |
| dc.contributor.author | Yankey, Jephthah | |
| dc.contributor.author | Addo, Ernest Ofosu | |
| dc.contributor.author | Agbemenu, Andrew Selasi | |
| dc.contributor.author | Tchao, Eric Tutu | |
| dc.contributor.author | Akowuah, Bright Yeboah | |
| dc.date.accessioned | 2024-05-17T14:30:30Z | |
| dc.date.available | 2024-05-17T14:30:30Z | |
| dc.date.issued | 2022-10-28 | |
| dc.description.abstract | This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect-oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40–100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of −132 dBc/Hz at 1 MHz and consumes 1.8mWon a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6μ complementary metal-oxide-semiconductor process. | |
| dc.identifier.other | https://doi.org/10.1049/tje2.12211 | |
| dc.identifier.uri | https://ir.knust.edu.gh/handle/123456789/15707 | |
| dc.language.iso | en_US | |
| dc.publisher | The Journal of Engineering | |
| dc.title | Design of a fully integrated VHF CP-PLL frequency synthesizer with an all-digital defect-oriented built-in self-test | |
| dc.type | Article |